High-voltage metal-oxide-semiconductor (HVMOS) devices are widely used in many electrical devices, such as input/output (I/O) circuits, CPU power supplies, power management systems, AC/DC converters, etc.
There are a variety of forms of HVMOS devices. A symmetric HVMOS device may have a symmetric structure on the source side and drain side. High voltage can be applied on both drain and source sides. An asymmetric HVMOS device may have asymmetric structures on the source side and drain side. For example, only one of the source side and drain side, typically the drain side, is designed for sustaining high voltages.
FIG. 1 illustrates a conventional asymmetric HVNMOS device 2, which includes gate oxide 10, gate electrode 12 on gate oxide 10, drain region 4 in a high-voltage n-well region 1 (HVNW1), and a source region 6 in a high-voltage p-well region 1 (HVPW1). A shallow trench isolation (STI) region 8 spaces drain region 4 and gate electrode 12 apart so that a high drain-to-gate voltage can be applied.
HVNMOS device 2 is formed on a high-voltage anti-punch-through (APT) region 14, which is of p-type, and is referred to as an HVNAPT region 14, wherein the letter “N” indicates an n-type inversion region formed in HVNAPT region 14 during the operation of HNVMOS device 2. When a high voltage is applied to drain region 4, wherein the voltage can be as high as 20 volts, a high voltage is also applied to HVNW1 region. Assuming HVNAPT region 14 is not formed, and HVPW1 region and HVNW1 region are formed directly on p-substrate 16, the high voltage applied on drain region 4 will cause inversion regions (not shown) to be generated at the interface of HVNW1 region and p-substrate 16. On the HVNW1 region side, the inversion region is of p-type, and on the p-substrate 16 side, the inversion region is of n-type. Since p-substrate 16 is typically lightly doped, the inversion region in p-substrate 16 extends for a relatively great distance. The inversion region may be connected to another inversion region of HVNW2 region, which belongs to a neighboring HVNMOS device 18. A punch-through thus occurs. To solve this problem, a HVNAPT region 14 is formed underlying HVNMOS devices. Since HVNAPT regions are doped with a p-type impurity with a significantly greater concentration than in p-substrate 16, the thicknesses of the respective inversion regions are significantly less, and thus punch-through is prevented.
The conventional HVNMOS devices illustrated in FIG. 1 have drawbacks, however. FIG. 2 illustrates an I-V curve obtained from an HVNMOS device shown in FIG. 1, wherein the X-axis represents voltages applied on drain region 4, and the Y-axis represents drive currents. It is noted that if a high voltage Vg, for example, 20V, is applied, the drive currents do not saturate, or in other words, do not pinch, with the increase in drain voltages. This indicates an output resistance problem, which will cause device reliability problems. Therefore, a solution for the above-discussed problem is needed.